Leti introduced the development progress of GaN power electronics technology
“The French micro/nanotechnology research and development center CEA-Leti published two supplementary research papers at the 66th IEEE International Conference on Electronic Devices (IEDM 2020), which confirmed that its gallium nitride (GaN) technology method is expected to overcome various challenges. Advanced GaN devices embedded in MOS gates have more optimized architecture and performance, and are aimed at the rapidly growing global power conversion system market demand.
The French micro/nanotechnology research and development center CEA-Leti published two supplementary research papers at the 66th IEEE International Conference on Electronic Devices (IEDM 2020), which confirmed that its gallium nitride (GaN) technology method is expected to overcome various challenges. Advanced GaN devices embedded in MOS gates have more optimized architecture and performance, and are aimed at the rapidly growing global power conversion system market demand.
The researchers described various experiments on changes in high electron mobility transistors (HEMT) based on gallium nitride on silicon (GaN-on-Si). Compared with silicon, GaN-based semiconductors have simultaneously improved the performance and reliability of increasingly compact power converters, and AlGaN/GaN HEMTs have been shown to replace silicon or silicon carbide (SiC)-based power conversion solutions in high-frequency applications. The potential of the solution is low power consumption and low noise. Therefore, the technology is expected to become a cost-effective power conversion solution for many end-user applications, ranging from smart phones to kitchen appliances and electric vehicles, from battery management to DC/DC or AC/DC converters.
Taken together, these two papers provide a novel theory for the gate stack of the GaN MOS-c HEMT developed by CEA-Leti under the framework of IRT Nanoelec. They demonstrated the complexity of characterization of GaN MOS stacks and the expertise required to report and analyze reliable parameter values. The work proposed in these papers will also help solve the disadvantages of GaN devices to improve reliability, which is one of the main tasks of CEA-Leti in the process of industrialization transfer.
“Carbon-related pBTI degradation mechanism in GaN E-type MOSc-HEMT on Si”
The paper “Carbon-related pBTI degradation mechanism in GaN E-type MOSc-HEMT on silicon” studies the physics behind the positive temperature instability (pBTI) effect, which occurs when the transistor gate is positively biased , So as to determine the root cause of the phenomenon and minimize it.
The author of the paper, Aby-Gaël Viey, said: “We have confirmed that under positive gate stress, the instability of the voltage threshold (Vth) is caused by two traps. The first one is related to gate oxide defects. This is a known effect, and the second is related to the presence of carbon atoms in the nitrogen atoms in the GaN of the gate. This is a discovery and therefore confirms the conclusions put forward on the IEDM.”
Generally, in the MOS technology commonly used in BTI reliability testing (such as CMOS technology based on Si/SiGe/Ge), the root cause of Vth instability is related to oxide defects, which can be caused by the charge or discharge of electrons or holes , Depending on the device type (n/p-MOS) and bias polarity. As far as GaN MOS-c HEMT is concerned, the epitaxial structure grown under the transistor is very complex and far from uniform.
This study also confirmed the conclusion of the work reported by CEA-Leti in a paper on IEDM 2019 (“Research on nBTI degradation of GaN-on-Si E-type MOSc-HEMT’), and the results showed that GaN-in-N Carbon in[CN]It is usually introduced as a deep master to create a semi-insulating GaN layer for breakdown voltage management. Part of the BTI instability is related to common oxide trap charges. Therefore, the epitaxial structure is a significant factor in reducing and minimizing the instability in GaN power devices.
“In addition, our recent work has shown that these threshold voltage instabilities can be accurately modeled and predicted with high accuracy.” Viey said, “In fact, the known capture emission time (CET) model is used to confirm the two traps And predict the degradation (Vth drift) of pBTI under certain gate/temperature stress conditions.”
“A novel insight of interface trap density (Dit) extraction in Si-GaN MOS-c HEMT”
This research “novel insights into the interface trap density (Dit) extraction in GaN-on-Si MOS-c HEMT” aims to characterize the electrical quality of the oxide/GaN interface to understand the interface traps of the CEA-Leti gate stack Whether the density is the main threshold voltage (Vth) contributor in the GaN-on-Si MOS-c HEMT, and confirm the solution developed by the institute in the 10-year research and development process. “
The interface trap density (Dit) can extract the density of interface defects that are electrically active at the oxide/semiconductor interface and their distribution between the energy and the semiconductor band gap. Importantly, Vth is directly related to physical parameters that are easy to adjust (such as metal gate work function and semiconductor doping) and certain defect-related parameters (such as fixed or mobile charges of oxide and interface state density). If the interface is not properly passivated and processed, this density can greatly affect Vth.
In the case of GaN MOS-c HEMT, dry etching is performed on GaN. Oxide deposition and this aggressive process step may have a huge impact on the oxide/GaN interface in the future. Therefore, the development and optimization of MOS-based GaN power devices requires accurate and reliable interface characterization technology. “For other industries or researchers, this method will help assess the density of interface traps.” said William Vandendaele, the author of the paper.
Vandendaele said that CEA-Leti’s next step is to expand the team’s understanding of the gate stack optimization of GaN MOSc HEMT to minimize the Dit value and transfer the best products, processes and characterization methods to the IRT PowerGaN Institute. Partner.
CEA-Leti stated that it will follow its GaN roadmap through further research in epitaxy, devices, passive components, co-integration, and system architecture to develop GaN technology that can achieve switching frequency and power density up to that of silicon. 10 times, all use standard CMOS technology to reduce costs.
Part of this work was done in the framework of IRT Nanoelec.