# Low-cost, low-resolution solution for resolver signal processing

The resolver (resover) contains three windings, namely a rotor winding and two stator windings. The rotor winding rotates with the motor, the stator winding position is fixed and the two stators are at an angle of 90 degrees to each other (as shown in Figure 1). In this way, the winding forms a transformer with an angle-dependent coefficient.

Figure 1: Resolver and related signals

The sinusoidal carrier wave applied to the rotor winding is coupled to the stator winding, and the output of the stator winding is modulated with respect to the angle of the rotor winding. Due to the installation position, the phase difference of the modulated output signals of the two stator windings is 90 degrees. The angular position information of the motor can be obtained by demodulating the two signals. First, the pure sine wave and the cosine wave are received, and then divided to obtain the tangent value of the angle, and finally the angle value is obtained through the “arctangent” function. Since DSP is generally used for arithmetic processing, it is necessary to digitize sine and cosine waves. There are several special products with these functions on the market, but they are expensive, and other alternatives need to be sought for most applications. One of the most commonly used methods is to detect the peak of the carrier frequency in the output signal to trigger the analog-to-digital converter (ADC). If the modulation signal is always switched at this point in time, the carrier frequency will be eliminated. Because the higher resolution incremental accumulation (Δ-Σ) ADC always integrates and samples the signal over a period of time, it will not only convert the peak voltage, so it needs to use a successive approximation ADC such as TI ADS7861 or ADS8361 to resolve The rate is also limited to 12-14. This method also requires the use of several circuit modules, a suitable sinusoidal carrier must be generated, the conversion process must be triggered at a suitable point in time, and the ADC must convert the signal synchronously. This not only increases the cost, but also has limited resolution.

The new concept uses an over-sampling method and moves the demodulation to the digital domain. The over-sampling of the modulated signal uses the dual-channel delta-sigma modulator ADS1205, and the digital filter chip AMC1210 is used for demodulation and decimation of the modulator output. The modulator only generates a bit stream, which is different from the digital concept in ADCs. In order to output a digital signal equivalent to the analog input voltage, a digital filter must be used to process the bit stream. The sine filter is a very simple, easy to construct and minimal hardware requirement. Those signals whose frequencies are integer multiples of the modulator clock frequency divided by the oversampling rate will be suppressed. These suppressed frequency points are called notches. In this new concept, the principle of setting the decimation rate of the integrator is to make the carrier frequency fall into a certain notch frequency. But the signal needs to be demodulated first, otherwise the angle information will be ignored along with the carrier frequency. This task is completed by AMC1210. AMC1210 has four channels, and each channel provides the filter structure shown in Figure 2.

Figure 2: Digital filter structure of AMC1210

AMC1210 can also be used to measure current. In this example, we use a comparator filter for over-current protection, which can achieve fast response at low resolution (shown in blue in the figure). The $ part can produce a higher resolution output at a lower sampling rate, and this part is used in the control loop. According to the needs of the application, sine filters and integrators can be used here to optimize the structure of the filter. In addition, this path can also be used for filtering and demodulation. First, the sine filter in the AMC1210 filters the bit stream of the modulator to convert it into a medium-resolution, medium-rate data word. For ADS1205, the most efficient third-order sine filter has an oversampling rate (OSR) of 128. When the oversampling rate exceeds 128, the signal-to-noise ratio only increases by 3dB for every doubling of the OSR. The same effect can be achieved by using an integrator after the demodulation process, and the delay time of the filter can also be shortened. When OSR is set to 128, a 14-bit digital modulation signal will be generated, and its data rate is:

In the equation, fmod represents the clock frequency of the modulator, which is reduced to half of the original clock frequency in the modulator. In the following example, when the clock signal frequency is 32.768MHz, the data rate of the third-order sine filter is 128kHz. Now the signal needs to be demodulated (as shown in Figure 3).

Figure 3: Example of demodulation process inside AMC1210

This means that when the unmodulated carrier is positive, the 14-bit digital signal must be multiplied by +1, and if the unmodulated carrier is negative, it must be multiplied by -1. We need to consider the delay caused by the carrier signal passing through the resolver, coil, modulator, and sine filter. Therefore, AMC1210 has a phase shift check function and can work normally within a phase shift of 90 degrees. If the phase shift exceeds this range, it must be programmed in the register. Finally, the setting principle of the integrator OSR is: the carrier frequency is an integer multiple of the notch of the entire filter transfer function. In the time domain, this is equivalent to integrating over multiple carrier periods. This completely suppresses the carrier frequency. In this example, if the OSR of the integrator is 16, the resolution is increased by 2 bits (0.5 bits/factor 2). However, the amplitude of the output signal is reduced by 3dB (-0.5 bits) because the integrator produces the average voltage of the demodulated signal instead of the peak voltage. Summary: The output of AMC1210 is digital sine wave or cosine wave, the data rate is 8kHz, and the noise performance is 15.5 bits. The amplitude of this signal is 3dB lower than the input modulation signal.

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