How to start with PCB layout to avoid noise caused by improper layout of switching power supply
““Noise problem!” – those are the words every board designer hears. In order to solve the noise problem, it often takes hours of laboratory testing to find the culprit, but it turns out that the noise is caused by the improper layout of the switching power supply. Addressing such issues may require designing new layouts, resulting in product delays and increased development costs.
“Noise problem!” – those are the words every board designer hears. In order to solve the noise problem, it often takes hours of laboratory testing to find the culprit, but it turns out that the noise is caused by the improper layout of the switching power supply. Addressing such issues may require designing new layouts, resulting in product delays and increased development costs.
This article will provide guidelines on printed circuit board (PCB) layout to help designers avoid such noise problems. The example switching regulator layout uses the ADP1850 dual-channel synchronous switching controller. The first step is to determine the current path for the regulator. The current path then determines the placement of the device in this low noise place and route design.
PCB Layout Guidelines
Step 1: Determine the current path
In switching converter designs, the high and low current paths are very close to each other. The alternating current (AC) path carries spikes and noise, the high direct current (DC) path creates a considerable voltage drop, and the low current path tends to be sensitive to noise. The key to proper PCB layout is to determine the critical path, then arrange the device, and provide enough copper area so that the high current does not destroy the low current. Poor performance is ground bounce and noise injection into the rest of the IC and system.
Figure 1 shows a synchronous buck regulator design that includes a switching controller and the following external power components: high-side switch, low-side switch, Inductor, input capacitor, output capacitor, and bypass capacitor. The arrows in Figure 1 indicate the flow of high switching currents. These power components must be placed carefully to avoid undesirable parasitic capacitances and inductances that can cause excessive noise, overshoot, ringing, and ground bounce.
Figure 1. Typical Switching Regulator (AC and DC Current Paths Shown)
Switching current paths such as DH, DL, BST, and SW need to be routed out of the controller to avoid excessive parasitic inductance. These lines carry high deltaI/deltat AC switching pulse currents that can reach over 3 A for nanoseconds. The high-current loop must be small to minimize output ringing and avoid picking up additional noise.
Low-value, low-amplitude signal paths, such as compensation and feedback devices, are sensitive to noise. These paths should be kept away from switching nodes and power devices to avoid injecting unwanted noise.
Step 2: Layout Physical Plan
The floor plan of the PCB is very important. The area of the current loop must be minimized, and the power supply devices must be properly arranged to make the current flow smoothly and avoid sharp corners and narrow paths. This will help reduce parasitic capacitance and inductance, thereby eliminating ground bounce.
Figure 2 shows the PCB layout of a dual-output buck converter using the switching controller ADP1850. Note that the layout of the power device minimizes current loop area and parasitic inductance. Dashed lines indicate high current paths. Both synchronous and asynchronous controllers can use this physical planning technique. In asynchronous controller designs, Schottky diodes replace low-side switches.
Figure 2. PCB Layout of Dual Output Buck Converter Using ADP1850 Controller
Step 3: Power Devices – MOSFETs and Capacitors (Input, Bypass and Output)
The current waveform at the top and bottom power switches is a pulse with a very high deltaI/deltat. Therefore, the paths connecting the switches should be kept as short as possible to minimize noise picked up by the controller and transmitted by the inductive loop. When using a pair of DPAK or SO-8 packaged FETs on one side of the PCB, it is best to rotate the two FETs in opposite directions so that the switch node is on one side of the pair of FETs and bypass the high-side with a suitable ceramic bypass capacitor. The leakage current is bypassed to the low-side source. Be sure to place the bypass capacitor as close to the MOSFET as possible (see Figure 2) to minimize inductance around the loop through the FET and capacitor.
The placement of input bypass capacitors and input bulk capacitors is critical to controlling ground bounce. The negative connection of the output filter capacitor should be as close as possible to the source of the low-side MOSFET to help reduce the loop inductance that causes ground bounce. Cb1 and Cb2 in Figure 2 are ceramic bypass capacitors, and the recommended value range for these capacitors is 1 μF to 22 μF. For high current applications, an additional larger value filter capacitor should be connected in parallel, as shown by CIN in Figure 2.
Thermal Considerations and Ground Planes
Under heavy load conditions, the equivalent series resistance (ESR) of power MOSFETs, inductors, and bulk capacitors can generate significant amounts of heat. For efficient heat dissipation, the example of Figure 2 places a large area of copper under these power devices.
The heat dissipation effect of multi-layer PCB is better than that of 2-layer PCB. For improved thermal and electrical conductivity, 2 oz thick copper should be used over a standard 1 oz copper layer. It would also help to have multiple PGND layers connected together via vias. Figure 3 shows a 4-layer PCB design with PGND layers distributed across the top, third, and fourth layers.
Figure 3. Cross-Section: Connecting PGND Layers to Improve Thermal Dissipation
This multiple ground plane approach isolates noise-sensitive signals. As shown in Figure 2, the negative terminals of the compensation device, soft-start capacitor, bias input bypass capacitor, and output feedback divider resistor are all connected to the AGND plane. Do not connect any high current or high deltaI/deltat paths directly to the isolated AGND plane. AGND is a quiet ground plane where no large current flows.
The negative terminals of all power devices (such as low-side switches, bypass capacitors, input and output capacitors, etc.) are connected to the PGND plane, which carries high currents.
The voltage drop in the GND plane can be so large that it affects the output accuracy. Connecting the AGND plane to the negative side of the output capacitor with a wide trace (see Figure 4) can significantly improve output accuracy and load regulation.
Figure 4. Connection of AGND plane to PGND plane
The AGND layer extends all the way to the output capacitor, and the AGND and PGND layers are connected to vias at the negative end of the output capacitor.
Figure 2 shows another technique for connecting the AGND and PGND layers. The AGND layer is connected to the PGND layer through a via near the negative terminal of the output bulk capacitor. Figure 3 shows a cross-section of a location on the PCB where the AGND and PGND layers are connected by vias near the negative terminal of the output bulk capacitor.
Current detection path
To avoid degraded accuracy caused by disturbing noise, the current-sense path layout of the current-mode switching regulator must be appropriate. Dual-channel applications in particular pay more attention to eliminating any channel-to-channel crosstalk.
The ADP1850 dual buck controller uses the on-resistance RDS(ON) of the low-side MOSFET as part of the control loop architecture. This architecture senses the current through the low-side MOSFET between the SWx and PGNDx pins. Ground current noise in one channel can couple into adjacent channels. Therefore, it is important to keep the SWx and PGNDx traces as short as possible and place them close to the MOSFETs for accurate current sensing. The connections to the SWx and PGNDx nodes must be Kelvin sensing, as shown in Figure 2 and Figure 5. Note that the corresponding PGNDx traces are connected to the source of the low-side MOSFET. Do not arbitrarily connect the PGND plane to the PGNDx pins.
Figure 5. Grounding Technique for Two Channels
In contrast, for dual-channel voltage-mode controllers such as the ADP1829, the PGND1 and PGND2 pins are connected directly to the PGND plane through vias.
Feedback and Current-Limit Detection Paths
The FEEDBACK (FB) and LIMIT CURRENT (ILIM) pins are low signal level inputs, therefore, they are sensitive to capacitive and inductive noise interference. FB and ILIM traces should be avoided near high deltaI/deltat traces. Be careful not to allow the traces to form loops that increase undesirable inductance. Adding a small MLCC decoupling capacitor (eg, 22 pF) between the ILIM and PGND pins can help filter the noise further.
In a switching regulator circuit, the switch (SW) node is the most noisy place because it carries large AC and DC voltages/currents. This SW node requires a larger area of copper to minimize resistive voltage drop. Placing the MOSFET and inductor close to each other on the copper layer minimizes series resistance and inductance.
Applications that are more sensitive to EMI, switch node noise, and ringing can use a small snubber. The snubber consists of a resistor and capacitor in series (see RSNUB and CSNUB in Figure 6) and is placed between the SW node and the PGND plane to reduce ringing and EMI on the SW node. Note that adding snubbers may slightly decrease overall efficiency by 0.2% to 0.4%.
Figure 6. Buffer and Gate Resistor Resistors
gate driver path
The gate drive traces (DH and DL) also deal with high deltaI/deltat, which tends to produce ringing and overshoot. These traces should be as short as possible. It is best to route directly and avoid feed-through vias. If vias must be used, use two vias per trace to reduce peak current density and parasitic inductance.
A small resistor (about 2 Ω to 4 Ω) in series with the DH or DL pin can slow down the gate drive, which also reduces gate noise and overshoot. Alternatively, a resistor can be connected between the BST and SW pins (see Figure 6). Reserving space with 0 Ω gate resistors during layout increases flexibility for later evaluation. The increased gate resistance prolongs the gate charge rise and fall times, resulting in higher switching power losses in the MOSFET.
Understanding current paths, their sensitivities, and proper device placement is the key to eliminating noise problems in PCB layout designs. All of Analog Devices’ power device evaluation boards follow the placement and routing guidelines described above to achieve optimum performance. Evaluation board documents UG-204 and UG-205 detail the placement and routing of the ADP1850.
Note that all switching power supplies have the same components and similar current path sensitivities. Therefore, the same guidelines as described using the ADP1850 for a current-mode buck regulator apply to the placement and routing of voltage-mode and/or boost switching regulators.